The invention relates to an integrated circuit comprising a semiconductor body having a major surface at which plural circuit elements are present, wherein the semiconductor body has near the major surface a first substrate region of a first conductivity type and a second substrate region of a second conductivity type, the first substrate region comprising a source and a drain zone of the second conductivity type of at least a first field effect transistor, a first channel region extending between these source and drain zones and at the major surface being covered by an insulating layer. A first gate electrode comprising semiconductor material is present on this insulating layer, and the second substrate region comprises a source and a drain zone of the first conductivity type of at least a second field effect transistor, a second channel region extending between these source and drain zones and at the major surface being covered by an insulating layer, and a second gate electrode comprising semiconductor material being present on this insulating layer, the semiconductor material of the first gate electrode and the semiconductor material of the second gate electrode being of opposite conductivity types.
Such an integrated circuit is known from U.S. Pat. No. 3,673,471 published on June 27th, 1972. In this known integrated circuit, the conductivity types of the first and the second gate electrode are the same as the conductivity type of the source and drain zones of the first field effect transistor and the conductivity type of the source and drain zones of the second field effect transistor, respectively. It is further known from U.S. Pat. No. 3,673,471 that the threshold voltage of a field effect transistor having an insulated gate of amorphous semiconductor material depends upon the conductivity type and upon the doping concentration of the amorphous semiconductor material.
The proposals according to the aforementioned U.S. Pat. No. 3,673,471 date from the early years of silicon gate technology. In those times it was usual to dope the gate electrodes simultaneously with the formation of the source and drain zones. In later years, and especially after the introduction of the ion implantation technique, that method of doping the gate electrodes was entirely driven out by a method in which the amorphous or polycrystalline semiconductor layer is n-doped with a high doping concentration during and/or immediately after the deposition. In the manufacture of CMOS circuits, this n-type semiconductor layer is now generally used for both types of field effect transistors, the threshold voltages of these field effect transistors being adjusted to the desired value by means of accurate implantation of a suitable dopant in the channel region. In this modified form, the silicon gate technology is thus far the essential part of the method of manufacturing integrated circuits comprising insulated gate field effect transistors.
It should be noted that in integrated circuits comprising complementary insulated gate field effect transistors the absolute values of the threshold voltages of the n-channel and the p-channel transistors are generally chosen to be substantially equal. These threshold voltages depend inter alia upon the doping concentration in the relevant substrate region, upon the quality, the composition and the thickness of the insulating layer constituting the relevant gate dielectric, upon the difference in work function of the semiconductor material of the substrate region and of the material of which the relevant gate electrode is made, and upon the doping concentration of the aforementioned implantation in the channel region. The said implantation treatment in practice has the great advantage that it provides the freedom to make a choice considered to be more or less optimal for each of the remaining parameters within wide limits in virtue of other dependences, such as the influence on the mutual conductance, on the value of (parasitic) capacitance and on the series resistance in the gate electrodes and/or the technological possibilities, and then to adapt the doping concentration of the implantation treatment to the choice made in a manner such that the threshold voltages of the transistors obtain the desired values which in absolute sense are substantially equal to each other.
Meanwhile, the dimensions of the field effect transistors used in integrated circuits have become increasingly smaller in the course of time. It has been found that particular effects are obtained in field effect transistors having very small dimensions. Thus, in field effect transistors having a small channel length of, for example, less than 3 .mu.m the threshold voltage also depends upon this channel length. The term "channel length" is generally to be understood to mean the distance in the channel region between source and drain zone. In silicon gate technology, this channel length is directly derived from the width of the semiconductor track of the gate electrode.
When the field effect transistor structures used are further reduced in scale, so-called short-channel effects can be taken into account. Thus, the undesired decrease of the threshold voltage associated with a further reduction of the channel length can be counteracted entirely or in part by the use of the doping dose of the implantation by means of which the threshold voltage is adjusted.
A particularly disadvantageous consequence of shortchannel effects is that the threshold voltages of the transistor become sensitive to small variations in the manufacturing process and notably to small variations in the width of the semiconductor tracks constituting the gate electrodes.